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GR5526 series

GR5526 series is a high-performance, low-power System-on-Chip (SoC) family supporting Bluetooth 5.3 Low Energy. The series allows users to develop Bluetooth Low Energy (Bluetooth LE) applications and products serving as a Central and/or a Peripheral, perfectly addressing your growing demands for faster compute capability, higher graphics display/processing performance, and more scalability in smart wearables, human interface devices (HIDs), Internet of Things (IoT) applications, and other innovative devices.
Packaging: QFN/BGA
Qualified Information
SIG BQB Qualified
Product Brief
GR5526 Product Brief

Overview

The GR5526 series is a single-mode, low-power Bluetooth 5.3 System-on-Chip (SoC) centering on ARM® Cortex®-M4F core with up to 96 MHz clock frequency. The series outperforms counterparts not only for its integrated angle of arrival (AoA), angle of departure (AoD), and LE Audio features, but wearable-oriented capabilities such as enhanced display performance, 2.5D GPU, Display Control (DC) module, and built-in PSRAM. All of these make GR5526 an ideal choice for smart wearables, human interface devices (HIDs), Internet of Things (IoT) applications, and more.

Part Number
CPU
RAM
SiP Flash
SiP PSRAM
GPU+DC
I/O Number
Package (mm)
  • GR5526VGBIP
    Cortex®-M4F
    512 KB
    1 MB
    8 MB
    Supported
    50
    BGA83(4.3 * 4.3 * 0.96)
  • GR5526VGBI
    Cortex®-M4F
    512 KB
    1 MB
    N/A
    N/A
    50
    BGA83(4.3 * 4.3 * 0.96)
  • GR5526RGNIP
    Cortex®-M4F
    512 KB
    1 MB
    8 MB
    Supported
    48
    QFN68(7.0 * 7.0 * 0.85)
  • GR5526RGNI
    Cortex®-M4F
    512 KB
    1 MB
    N/A
    N/A
    48
    QFN68(7.0 * 7.0 * 0.85)

* Note:

  1. GR5526 series only for preview.

Features

  • Bluetooth Low Energy 5.3 transceiver integrating Controller and Host layers

    • Supported data rates: 1 Mbps, 2 Mbps, and Long Range (500 kbps, 125 kbps)
    • TX power: -20 dBm to +7 dBm
    • -98 dBm sensitivity (in 1 Mbps mode)
    • -94 dBm sensitivity (in 2 Mbps mode)
    • -101 dBm sensitivity (in Long Range 500 kbps mode)
    • -104 dBm sensitivity (in Long Range 125 kbps mode)
    • TX current: 4.0 mA @ 0 dBm, 1 Mbps
    • RX current: 3.5 mA @ 1 Mbps
    • AoA/AoD, Ranging, LE Isochronous Channels
  • ARM® Cortex®-M4F 32-bit micro-processor with floating point support

    • Up to 96 MHz clock frequency
    • Built-in Memory Protection Unit (MPU) supporting eight programmable regions
    • Hardware Floating Point Unit (FPU)
    • Built-in Nested Vectored Interrupt Controller (NVIC)
    • Non-maskable Interrupt (NMI) input
    • Serial Wire Debug (SWD) with 16 breakpoints, two watchpoints, and a debug timestamp counter
    • 51 µA/MHz execution from Flash @ 3.3 V, 96 MHz
  • On-chip memory

    • 512 KB data SRAM with retention capabilities
    • 8 KB cache SRAM with retention capabilities
    • Stack ROM (including boot ROM and Bluetooth LE Stack)
    • 1 MB internal QSPI Flash
    • 8 MB internal PSRAM (for GR5526VGBIP and GR5526RGNIP only)
  • Digital peripherals

    • Two general-purpose DMA engines, each with 6 channels and up to 16 programmable request/trigger sources
    • USB 2.0 full speed (12 Mbps) controller with on-chip PHY and dedicated DMA controller
    • Internal Octal SPI DDR interfaces to support 8 MB internal PSRAM at up to 48 MHz (for GR5526VGBIP and GR5526RGNIP only)
  • Power management

    • On-chip DC-DC to provide RF Analog voltage and supply core LDO
    • On-chip I/O LDO to provide I/O voltage and supply external components, maximum I/O LDO drive strength: 30 mA
    • Programmable thresholds for brownout detection (BOD)
    • Supply voltage: 2.4 V–4.35 V
    • I/O voltage: 1.8 V–3.6 V
  • Low-power consumption modes

    • Sleep mode: 3.1 µA at 3.3 V VBAT input with 128 KB SRAM retention on and LFXO_32K off; woken up by 8 sources of always-on domain
    • OFF mode: 200 nA; nothing on except VBAT, and chip in reset mode
  • Packages

    • BGA83: 4.3 mm * 4.3 mm, 0.4 mm pitch
    • QFN68: 7.0 mm * 7.0 mm, 0.35 mm pitch
  • Operating temperature range

    • -40 °C to +85 °C
  • Analog peripherals

    • One 13-bit Sense ADC with a sampling rate of 1 Msps. It supports up to 8 external I/O channels and 3 internal signal channels
    • Built-in temperature and voltage sensors
    • Low-power comparator, supporting wakeup from deep sleep mode
  • Flexible serial peripherals

    • 6 * UART modules up to 4 Mbps, with all modules supporting flow control and IrDA
    • 6 * I2C modules for peripheral communication, up to 3.4 MHz
    • 1 * 8-bit/16-bit/32-bit SPI master interface and 1 * SPI slave interface for host communication
    • 2 * I2S interfaces (1 I2S master interface and 1 I2S slave interface)
    • PDM interface with hardware sampling rate converter
    • 1 * ISO7816 interface
  • Display/Graphics

    • 1 * Dual-lane SPI (DSPI) interface for display, with MIPI (Mobile Industry Processor Interface) DSI (Display Serial Interface) Type-C support
    • 3 * Quad SPI (QSPI) interfaces, running at frequencies of up to 48 MHz; supporting fast access to Flash/PSRAM, made possible by Execute-In-Place (XIP) and address-remapping
    • Display Control (DC) module with MIPI DSI Type-C support and 2D graphics blending integrated (for GR5526VGBIP and GR5526RGNIP only)
    • 2.5D GPU for graphics acceleration (for GR5526VGBIP and GR5526RGNIP only)
  • Security

    • Complete secure computing engine:
      • AES 128-bit/192-bit/256-bit encryption (ECB and CBC)
      • Hash-based Message Authentication Code (HMAC-SHA256)
      • Public key cryptography (PKC)
      • True random number generator (TRNG)
    • Comprehensive security operation mechanism:
      • Secure boot
      • Encrypted firmware runs directly from Flash
      • Fuse for encrypted key storage
      • Differentiate application data key and firmware key, supporting one data per device/product
  • I/O Peripherals

    • Up to 50 multiplexed I/O pins in total
      • Up to 34 general-purpose I/O(GPIO) pins
      • Up to 8 always-on I/O(AON IO) pins, supporting wakeup from deep sleep mode
      • Up to 8 mixed signal I/O(MSIO) pin, configurable to be digital/analog signal interfaces
  • Timer

    • Two general-purpose, 32-bit timer modules
    • A timer module composed of two programmable 32-bit or 16 bit down counters
    • An internal sleep timer that can be used to wake the device up from deep sleep mode
    • 2 PWM modules with edge alignment mode and center alignment mode, each with 3 channels
    • 2 * real-time counters (RTC): 1 * Calendar, 1 * RTC

System Block Diagram

  • Bluetooth Subsystem

    1. A 2.4 GHz transceiver and a digital communication module supporting Bluetooth 5.3
  • MCU Subsystem

    1. An ARM® Cortex®-M4F core and a 2.5D GPU with all necessary memories and peripherals
    2. Security Cores for application protection and secure boot execution
    3. GPU + DC to enhance processing capabilities
  • Power Management Unit (PMU) Subsystem

    1. All the required power management modules to supply sufficient power for both internal modules and external peripherals
    2. Modules required for ultra-low-power operation are in standby mode. HFRC_192M, RNG_OSC, LFRC_32K, wakeup GPIOs (Wake up), low-power comparator (LP Comp.), and power state controller (Power Sequencer) are used to control the state of different modules

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