603160.SH

Log In

603160.SH

GM6x5x Series – A Microcontroller Unit Family Which Integrates Hardware Fingerprint Algorithm with High Performance and Low Power Consumption

Overview

The GM6x5x series microcontroller (MCU) has high performance and consumes very less power. It integrates a hardware fingerprint algorithm accelerator internally and is equipped with excellent fingerprint authentication algorithm performance and adaptability to different conditions.

The GM6x5x series comes in three different models: GM6256, GM6451PBNI and GM6451SBBIF. Among these three, GM6256 has an in-built security algorithm module and has cleared the EAL4+ security certification while complying with the ICA alliance’s ID2 security application order and guidelines. In addition, GM6256 and GM6451PBNI offer the QFN packaging and GM6451SBBIF offers the BGA packaging.

Features

  • CPU

    • Fully support the RV32I basic instruction set
    • Fully support the RV32C standard extended compression instruction set
    • Fully support the RV32M extended instruction set of the internally integrated multiplier and divider
    • Fully support the RV32F single-precision floating-point extended instructions
    • Special extended instructions include:
      • Backward loading and storage
      • Support extended multiplication and addition
      • Support extended arithmetic logic units (ALU)
  • On-chip storage

    • Instruction ROM (IROM): 128 KB
    • Data ROM (DROM): 32 KB
    • Instruction RAM (IRAM): 128 KB
    • Data RAM (DRAM): 64 KB
    • Cache RAM (BRAM):192 KB
    • eFuse: 4,096 bits
  • Functional modules

    • On-chip image with hardware acceleration algorithm module, These mainly include the pre-processing algorithm, feature extraction algorithm and matching algorithm
      • The modules include 13 hardware acceleration operators and software serial calls
      • Command queue method calls operators
      • MOC (Match on chip) accesses buffer RAM through Local bus
      • Completion interrupts can be sent after command queues execution is completed
    • Supports two channels of DMA
    • 2 Timers
    • 1 Watchdog
    • 1 interrupt controller
    • 1 RTC
  • Security modules (some of the functions are supported by GM6256 only)

    • Supports AES-128/192/256
    • Supports HMAC-SHA256
    • Supports ECC-256/RSA-2048
    • Support true randomness/pseudo randomness, including:
      • FRO ring oscillator digital true randomness source and analogue chaos switch current true randomness source
      • Digital random number post-processing unit
    • light, voltage and temperature safety sensors
  • Peripheral modules

    • 1 Flash controller, which has QSPI interfaces, with the maximum communication speed at 48 Mbps
    • 1 channel of QSPI Master, with maximum communication speed at 24 Mbps
    • 1 channel of SPI Master, with maximum communication speed at 24 Mbps
    • 1 channel of SPI Slave, with maximum communication speed at 24 Mbps
    • At most three channels of UART interfaces, with highest supported Baud rate of 115,200 baud/s
    • Supports up to 45 configurable GPIO (all of which can be used as interrupt inputs with only two supporting input directions)
    • 1 channel of I2C master device interface, with the maximum communication speed at 400 Kbps
    • JTAG debut port
  • Simulation features

    • Internally integrated 48 MHz and 32 kHz oscillators
    • Support external 12 MHz and 32 kHz crystal oscillator inputs
    • Integrated power management module
    • Integrated power-on reset and power-down reset modules
    • Integrated security sensors
    • Integrated switch current random number generator
    • Integrated 3 channels of LED drivers

System Block Diagram

Scan to follow

Open WeChat, click "Discover" at the bottom, and use "Scan" to follow.

×